Eecient Block Scheduling for Programmable Embedded Processors

Scheduling is probably the most often addressed optimization problem in DSP compilation, behav-ioral synthesis, and system-level synthesis research. With the rapid pace of changes in modern DSP applications requirements and implementation technologies, however, new types of scheduling challenges arise. This paper is concerned with the problem of scheduling blocks of computations in order to optimize the eeciency of their execution on programmable embedded systems under a realistic timing model of their processors. We describe an eeective scheme for scheduling the blocks of any computation on a given system architecture and with a speciied algorithm implementing each block. We also present algorith-mic techniques for performing optimal block scheduling simultaneously with optimal architecture and algorithm selection. Our techniques address the block scheduling problem for both single-and multiple-processor system platforms and for a variety of optimization objectives including through-put, cost, and power dissipation. We demonstrate the practical eeectiveness of our techniques on numerous examples.